Changeset 3525

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Timestamp:
09/11/06 17:30:13
Author:
matt
Message:

xilinx files, which are mostly generated by xilinxgen
Makefile thanks to jcorgan

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  • usrp-hw/trunk/sym/generated/xilinxgen

    r3522 r3525  
    3232''' 
    3333 
    34 configfile = open ('xc3sXX00FG456-CFG.src', 'w') 
     34configfile = open ('xc3sXX00fg456-CFG.src', 'w') 
    3535configfile.write(boilerplate % ("CFG",)) 
    3636 
    37 jtagfile = open ('xc3sXX00FG456-JTAG.src', 'w') 
     37jtagfile = open ('xc3sXX00fg456-JTAG.src', 'w') 
    3838jtagfile.write(boilerplate % ("JTAG",)) 
    39 powerfile = open ('xc3sXX00FG456-PWR.src', 'w') 
     39powerfile = open ('xc3sXX00fg456-PWR.src', 'w') 
    4040powerfile.write(boilerplate % ("PWR",)) 
    41 clockfile = open ('xc3sXX00FG456-CLK.src', 'w') 
     41clockfile = open ('xc3sXX00fg456-CLK.src', 'w') 
    4242clockfile.write(boilerplate % ("CLK",)) 
    43 vreffile = open ('xc3sXX00FG456-VREF.src', 'w') 
     43vreffile = open ('xc3sXX00fg456-VREF.src', 'w') 
    4444vreffile.write(boilerplate % ("VREF",)) 
    4545 
    4646iofiles = [0] * 8 
    4747for i in range(8): 
    48     iofiles[i] = open ( ('xc3sXX00FG456-IO%d.src' % (i,)), 'w') 
     48    iofiles[i] = open ( ('xc3sXX00fg456-IO%d.src' % (i,)), 'w') 
    4949    iofiles[i].write(boilerplate % ('IO%d' % (i,),)) 
    5050     
    …… 
    7272        writepin(powerfile,elements[3],elements[6],'line','pwr','l') 
    7373    elif(pintype == 'VCCO'): 
    74         writepin(powerfile,elements[3],elements[6],'line','pwr','t') 
     74        writepin(powerfile,elements[3],elements[6],'line','pwr','l') 
    7575    elif(pintype == 'VCCINT'): 
    76         writepin(powerfile,elements[3],elements[6],'line','pwr','b') 
     76        writepin(powerfile,elements[3],elements[6],'line','pwr','l') 
    7777 
    7878    elif(pintype == 'JTAG'): 
    …… 
    105105    else: 
    106106        print elements 
    107  
    108  
    109  
    110     #vreffile.write("%s\t\tio\tpwr\tl\t\t%s/400-NC\n" % (elements[3],elements[6])) 
    111 #iofiles[int(elements[12])].write("%s\t\tio\tline\tl\t\t%s/400-NC\n" % (elements[3],elements[6])) 
    112 #iofiles[int(elements[12])].write("%s\t\tio\tline\tl\t\t%s\n" % (elements[3],elements[4])) 
    113         #iofiles[int(elements[12])].write("%s\t\tio\tline\tl\t\t%s/DCI\n" % (elements[3],elements[4])) 
    114         #vreffile.write("%s\t\tio\tpwr\tl\t\t%s\n" % (elements[3],elements[4])) 
    115         #powerfile.write("%s\t\tpwr\tline\tr\t\t%s\n" % (elements[3],elements[4])) 
    116         #powerfile.write("%s\t\tpwr\tline\tl\t\t%s\n" % (elements[3],elements[4])) 
    117         #powerfile.write("%s\t\tpwr\tline\tt\t\t%s\n" % (elements[3],elements[4])) 
    118         #powerfile.write("%s\t\tpwr\tline\tb\t\t%s\n" % (elements[3],elements[4])) 
    119         #jtagfile.write("%s\t\tio\tline\tl\t\t%s\n" % (elements[3],elements[4])) 
    120         #configfile.write("%s\t\tio\tline\tl\t\t%s\n" % (elements[3],elements[4])) 
    121         #configfile.write("%s\t\tio\tline\tr\t\t%s\n" % (elements[3],elements[4])) 
    122         #clockfile.write("%s\t\tio\tclk\tl\t\t%s\n" % (elements[3],elements[4]))