Changeset 3820
- Timestamp:
- 10/19/06 01:17:37
- Files:
-
- usrp-hw/trunk/sym/generated/dp83865-CFGLED.src (modified) (1 diff)
- usrp-hw/trunk/sym/generated/dp83865-CLK.src (modified) (1 diff)
- usrp-hw/trunk/sym/generated/dp83865-JTAG.src (modified) (1 diff)
- usrp-hw/trunk/sym/generated/dp83865-MAC.src (modified) (3 diffs)
- usrp-hw/trunk/sym/generated/dp83865-MDI.src (modified) (1 diff)
- usrp-hw/trunk/sym/generated/dp83865-MGT.src (modified) (1 diff)
- usrp-hw/trunk/sym/generated/dp83865-PWR.src (modified) (2 diffs)
Legend:
- Unmodified
- Added
- Removed
- Modified
- Copied
- Moved
usrp-hw/trunk/sym/generated/dp83865-CFGLED.src
r3804 r3820 50 50 #pinnr seq type style posit. net label 51 51 #----------------------------------------------------- 52 1 in line l NON \_IEEE\_STRAP53 6 in line l MAN \_MDIX\_STRAP/TX\_TCLK54 7 io line r ACTIVITY \_LED/SPEED0\_STRAP55 8 io line r LINK10 \_LED/RLED/SPEED1\_STRAP56 9 io line r LINK100 \_LED/DUPLEX\_STRAP57 10 io line r LINK1000 \_LED/AN\_EN\_STRAP58 13 io line r DUPLEX \_LED/PHYADDR0\_STRAP59 14 in line l PHYADDR1 \_STRAP60 17 in line l PHYADDR2 \_STRAP61 18 in line l PHYADDR3 \_STRAP62 95 in line l PHYADDR4 \_STRAP63 94 io line l MULTI \_EN\_STRAP/TX\_TRIGGER64 89 io line l MDIX \_EN\_STRAP65 88 in line l MAC \_CLK\_EN\_STRAP/TX\_SYN\_CLK66 34 in line l VDD \_SEL\_STRAP52 1 in line l NON_IEEE_STRAP 53 6 in line l MAN_MDIX_STRAP/TX_TCLK 54 7 io line r ACTIVITY_LED/SPEED0_STRAP 55 8 io line r LINK10_LED/RLED/SPEED1_STRAP 56 9 io line r LINK100_LED/DUPLEX_STRAP 57 10 io line r LINK1000_LED/AN_EN_STRAP 58 13 io line r DUPLEX_LED/PHYADDR0_STRAP 59 14 in line l PHYADDR1_STRAP 60 17 in line l PHYADDR2_STRAP 61 18 in line l PHYADDR3_STRAP 62 95 in line l PHYADDR4_STRAP 63 94 io line l MULTI_EN_STRAP/TX_TRIGGER 64 89 io line l MDIX_EN_STRAP 65 88 in line l MAC_CLK_EN_STRAP/TX_SYN_CLK 66 34 in line l VDD_SEL_STRAP 67 67 usrp-hw/trunk/sym/generated/dp83865-CLK.src
r3804 r3820 50 50 #pinnr seq type style posit. net label 51 51 #----------------------------------------------------- 52 86 clk clk l CLK \_IN53 87 out line l CLK \_OUT54 85 out line l CLK \_TO\_MAC55 33 in line l _RESET_52 86 clk clk l CLK_IN 53 87 out line l CLK_OUT 54 85 out line l CLK_TO_MAC 55 33 in line l \_RESET\_ usrp-hw/trunk/sym/generated/dp83865-JTAG.src
r3804 r3820 50 50 #pinnr seq type style posit. net label 51 51 #----------------------------------------------------- 52 32 in dot l _TRST_52 32 in dot l \_TRST\_ 53 53 31 in line l TDI 54 54 28 out line l TDO usrp-hw/trunk/sym/generated/dp83865-MAC.src
r3804 r3820 50 50 #pinnr seq type style posit. net label 51 51 #----------------------------------------------------- 52 39 io line l COL/CLK \_MAC\_FREQ53 40 io line l CRS/RGMII \_SEL054 60 io line l TX \_CLK/RGMII\_SEL152 39 io line l COL/CLK_MAC\_FREQ 53 40 io line l CRS/RGMII_SEL0 54 60 io line l TX_CLK/RGMII_SEL1 55 55 76 in line r TXD0 56 56 75 in line r TXD1 … … 61 61 66 in line r TXD6 62 62 65 in line r TXD7 63 62 in line r TX \_EN/TX\_EN\ER64 79 in line r GTX \_CLK/TCK65 61 in line r TX \_ER66 57 out line l RX \_CLK63 62 in line r TX_EN/TX_EN\ER 64 79 in line r GTX_CLK/TCK 65 61 in line r TX_ER 66 57 out line l RX_CLK 67 67 56 out line l RXD0 68 68 55 out line l RXD1 … … 73 73 46 out line l RXD6 74 74 45 out line l RXD7 75 41 out line l RX \_ER/RXDV\ER76 44 out line l RX \_DV/RCK75 41 out line l RX_ER/RXDV\ER 76 44 out line l RX_DV/RCK 77 77 usrp-hw/trunk/sym/generated/dp83865-MDI.src
r3804 r3820 50 50 #pinnr seq type style posit. net label 51 51 #----------------------------------------------------- 52 108 io line r MDIA \_P53 109 io dot r _MDIA\_N_52 108 io line r MDIA_P 53 109 io dot r \_MDIA_N\_ 54 54 55 114 io line r MDIB \_P56 115 io dot r _MDIB\_N_55 114 io line r MDIB_P 56 115 io dot r \_MDIB_N\_ 57 57 58 120 io line r MDIC \_P59 121 io dot r _MDIC\_N_58 120 io line r MDIC_P 59 121 io dot r \_MDIC_N\_ 60 60 61 126 io line r MDID \_P62 127 io dot r _MDID\_N_61 126 io line r MDID_P 62 127 io dot r \_MDID_N\_ usrp-hw/trunk/sym/generated/dp83865-MGT.src
r3804 r3820 52 52 81 clk clk l MDC 53 53 80 io line l MDIO 54 3 io line l _INTERRUPT_54 3 io line l \_INTERRUPT\_ usrp-hw/trunk/sym/generated/dp83865-PWR.src
r3804 r3820 50 50 #pinnr seq type style posit. net label 51 51 #----------------------------------------------------- 52 4 pwr line l IO \_Vdd53 15 pwr line l IO \_Vdd54 21 pwr line l IO \_Vdd55 29 pwr line l IO \_Vdd56 37 pwr line l IO \_Vdd57 42 pwr line l IO \_Vdd58 53 pwr line l IO \_Vdd59 58 pwr line l IO \_Vdd60 69 pwr line l IO \_Vdd61 77 pwr line l IO \_Vdd62 83 pwr line l IO \_Vdd63 90 pwr line l IO \_Vdd52 4 pwr line l IO_Vdd 53 15 pwr line l IO_Vdd 54 21 pwr line l IO_Vdd 55 29 pwr line l IO_Vdd 56 37 pwr line l IO_Vdd 57 42 pwr line l IO_Vdd 58 53 pwr line l IO_Vdd 59 58 pwr line l IO_Vdd 60 69 pwr line l IO_Vdd 61 77 pwr line l IO_Vdd 62 83 pwr line l IO_Vdd 63 90 pwr line l IO_Vdd 64 64 65 11 pwr line l Core \_Vdd66 19 pwr line l Core \_Vdd67 25 pwr line l Core \_Vdd68 35 pwr line l Core \_Vdd69 48 pwr line l Core \_Vdd70 63 pwr line l Core \_Vdd71 73 pwr line l Core \_Vdd72 92 pwr line l Core \_Vdd65 11 pwr line l Core_Vdd 66 19 pwr line l Core_Vdd 67 25 pwr line l Core_Vdd 68 35 pwr line l Core_Vdd 69 48 pwr line l Core_Vdd 70 63 pwr line l Core_Vdd 71 73 pwr line l Core_Vdd 72 92 pwr line l Core_Vdd 73 73 74 101 pwr line l 2V5 \_Avdd175 96 pwr line l 2V5 \_Avdd274 101 pwr line l 2V5_Avdd1 75 96 pwr line l 2V5_Avdd2 76 76 77 103 pwr line l 1V8 \_AVdd178 105 pwr line l 1V8 \_AVdd179 111 pwr line l 1V8 \_AVdd180 117 pwr line l 1V8 \_AVdd181 123 pwr line l 1V8 \_AVdd177 103 pwr line l 1V8_AVdd1 78 105 pwr line l 1V8_AVdd1 79 111 pwr line l 1V8_AVdd1 80 117 pwr line l 1V8_AVdd1 81 123 pwr line l 1V8_AVdd1 82 82 83 98 pwr line l 1V8 \_AVdd284 100 pwr line l 1V8 \_AVdd383 98 pwr line l 1V8_AVdd2 84 100 pwr line l 1V8_AVdd3 85 85 86 86 5 pwr line r Vss … … 120 120 128 pwr line r Vss 121 121 122 102 in line b BG \_REF122 102 in line b BG_REF 123 123 2 in line l NC 124 124 23 in line l NC
