Implements a PLL which locks to the input frequency and outputs the input signal mixed with that carrier.
Input stream 0: complex Output stream 0: complex
This PLL locks onto a [possibly noisy] reference carrier on the input and outputs that signal, downconverted to DC
All settings max_freq and min_freq are in terms of radians per sample, NOT HERTZ. The loop bandwidth determins the lock range and should be set around pi/200 – 2pi/100.
Constructor Specific Documentation:
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Implements a PLL which locks to the input frequency and outputs an estimate of that frequency. Useful for FM Demod.
Input stream 0: complex Output stream 0: float
This PLL locks onto a [possibly noisy] reference carrier on the input and outputs an estimate of that frequency in radians per sample. All settings max_freq and min_freq are in terms of radians per sample, NOT HERTZ. The loop bandwidth determins the lock range and should be set around pi/200 – 2pi/100.
Constructor Specific Documentation:
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Implements a PLL which locks to the input frequency and outputs a carrier.
Input stream 0: complex Output stream 0: complex
This PLL locks onto a [possibly noisy] reference carrier on the input and outputs a clean version which is phase and frequency aligned to it.
All settings max_freq and min_freq are in terms of radians per sample, NOT HERTZ. The loop bandwidth determins the lock range and should be set around pi/200 – 2pi/100.
Constructor Specific Documentation:
Parameters: |
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