Include dependency graph for memory_map.h:
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Classes | |
| struct | spi_regs_t |
| struct | i2c_regs_t |
| struct | gpio_regs_t |
| struct | buffer_pool_status_t |
| struct | buffer_pool_ctrl_t |
| struct | output_regs_t |
| struct | dsp_tx_regs_t |
| struct | dsp_rx_regs_t |
| struct | tx_proto_engine_regs_t |
| struct | rx_proto_engine_regs_t |
| struct | pic_regs_t |
| struct | timer_regs_t |
| struct | uart_regs_t |
| struct | atr_regs_t |
| struct | timesync_regs_t |
| struct | sdspi_regs_t |
Defines | |
| #define | MASTER_CLK_RATE 100000000 |
| #define | RAM_BASE 0x0000 |
| #define | BUFFER_POOL_RAM_BASE 0x8000 |
| #define | NBUFFERS 8 |
| #define | BP_NLINES 0x0200 |
| #define | BP_LAST_LINE (BP_NLINES - 1) |
| #define | buffer_pool_ram ((uint32_t *) BUFFER_POOL_RAM_BASE) |
| #define | buffer_ram(n) (&buffer_pool_ram[(n) * BP_NLINES]) |
| #define | SPI_BASE 0xC000 |
| #define | spi_regs ((spi_regs_t *) SPI_BASE) |
| #define | SPI_SS_AD9510 1 |
| #define | SPI_SS_AD9777 2 |
| #define | SPI_SS_RX_DAC 4 |
| #define | SPI_SS_RX_ADC 8 |
| #define | SPI_SS_RX_DB 16 |
| #define | SPI_SS_TX_DAC 32 |
| #define | SPI_SS_TX_ADC 64 |
| #define | SPI_SS_TX_DB 128 |
| #define | SPI_CTRL_ASS (1<<13) |
| #define | SPI_CTRL_IE (1<<12) |
| #define | SPI_CTRL_LSB (1<<11) |
| #define | SPI_CTRL_TXNEG (1<<10) |
| #define | SPI_CTRL_RXNEG (1<< 9) |
| #define | SPI_CTRL_GO_BSY (1<< 8) |
| #define | SPI_CTRL_CHAR_LEN_MASK 0x7F |
| #define | I2C_BASE 0xC400 |
| #define | i2c_regs ((i2c_regs_t *) I2C_BASE) |
| #define | I2C_CTRL_EN (1 << 7) |
| #define | I2C_CTRL_IE (1 << 6) |
| #define | I2C_CMD_START (1 << 7) |
| #define | I2C_CMD_STOP (1 << 6) |
| #define | I2C_CMD_RD (1 << 5) |
| #define | I2C_CMD_WR (1 << 4) |
| #define | I2C_CMD_NACK (1 << 3) |
| #define | I2C_CMD_RSVD_2 (1 << 2) |
| #define | I2C_CMD_RSVD_1 (1 << 1) |
| #define | I2C_CMD_IACK (1 << 0) |
| #define | I2C_ST_RXACK (1 << 7) |
| #define | I2C_ST_BUSY (1 << 6) |
| #define | I2C_ST_AL (1 << 5) |
| #define | I2C_ST_RSVD_4 (1 << 4) |
| #define | I2C_ST_RSVD_3 (1 << 3) |
| #define | I2C_ST_RSVD_2 (1 << 2) |
| #define | I2C_ST_TIP (1 << 1) |
| #define | I2C_ST_IP (1 << 0) |
| #define | GPIO_BASE 0xC800 |
| #define | GPIO_SEL_SW 0 |
| #define | GPIO_SEL_ATR 1 |
| #define | GPIO_SEL_DEBUG_0 2 |
| #define | GPIO_SEL_DEBUG_1 3 |
| #define | gpio_base ((gpio_regs_t *) GPIO_BASE) |
| #define | BUFFER_POOL_STATUS_BASE 0xCC00 |
| #define | buffer_pool_status ((buffer_pool_status_t *) BUFFER_POOL_STATUS_BASE) |
| #define | BPS_DONE(n) (0x00000001 << (n)) |
| #define | BPS_DONE_0 BPS_DONE(0) |
| #define | BPS_DONE_1 BPS_DONE(1) |
| #define | BPS_DONE_2 BPS_DONE(2) |
| #define | BPS_DONE_3 BPS_DONE(3) |
| #define | BPS_DONE_4 BPS_DONE(4) |
| #define | BPS_DONE_5 BPS_DONE(5) |
| #define | BPS_DONE_6 BPS_DONE(6) |
| #define | BPS_DONE_7 BPS_DONE(7) |
| #define | BPS_ERROR(n) (0x00000100 << (n)) |
| #define | BPS_ERROR_0 BPS_ERROR(0) |
| #define | BPS_ERROR_1 BPS_ERROR(1) |
| #define | BPS_ERROR_2 BPS_ERROR(2) |
| #define | BPS_ERROR_3 BPS_ERROR(3) |
| #define | BPS_ERROR_4 BPS_ERROR(4) |
| #define | BPS_ERROR_5 BPS_ERROR(5) |
| #define | BPS_ERROR_6 BPS_ERROR(6) |
| #define | BPS_ERROR_7 BPS_ERROR(7) |
| #define | BPS_IDLE(n) (0x00010000 << (n)) |
| #define | BPS_IDLE_0 BPS_IDLE(0) |
| #define | BPS_IDLE_1 BPS_IDLE(1) |
| #define | BPS_IDLE_2 BPS_IDLE(2) |
| #define | BPS_IDLE_3 BPS_IDLE(3) |
| #define | BPS_IDLE_4 BPS_IDLE(4) |
| #define | BPS_IDLE_5 BPS_IDLE(5) |
| #define | BPS_IDLE_6 BPS_IDLE(6) |
| #define | BPS_IDLE_7 BPS_IDLE(7) |
| #define | BPS_SLOWPATH(n) (0x01000000 << (n)) |
| #define | BPS_SLOWPATH_0 BPS_SLOWPATH(0) |
| #define | BPS_SLOWPATH_1 BPS_SLOWPATH(1) |
| #define | BPS_SLOWPATH_2 BPS_SLOWPATH(2) |
| #define | BPS_SLOWPATH_3 BPS_SLOWPATH(3) |
| #define | BPS_SLOWPATH_4 BPS_SLOWPATH(4) |
| #define | BPS_SLOWPATH_5 BPS_SLOWPATH(5) |
| #define | BPS_SLOWPATH_6 BPS_SLOWPATH(6) |
| #define | BPS_SLOWPATH_7 BPS_SLOWPATH(7) |
| #define | BPS_DONE_ALL 0x000000ff |
| #define | BPS_ERROR_ALL 0x0000ff00 |
| #define | BPS_IDLE_ALL 0x00ff0000 |
| #define | BPS_SLOWPATH_ALL 0xff000000 |
| #define | HWC_SIMULATION 0x80000000 |
| #define | HWC_WB_CLK_DIV_MASK 0x0000000f |
| #define | ETH_BASE 0xD000 |
| #define | eth_mac ((eth_mac_regs_t *) ETH_BASE) |
| #define | MISC_OUTPUT_BASE 0xD400 |
| #define | TX_PROTOCOL_ENGINE_BASE 0xD480 |
| #define | RX_PROTOCOL_ENGINE_BASE 0xD4C0 |
| #define | BUFFER_POOL_CTRL_BASE 0xD500 |
| #define | DSP_TX_BASE 0xD600 |
| #define | DSP_RX_BASE 0xD680 |
| #define | LAST_SETTING_REG 0xD7FC |
| #define | PORT_SERDES 0 |
| #define | PORT_DSP 1 |
| #define | PORT_ETH 2 |
| #define | PORT_RAM 3 |
| #define | BPC_BUFFER(n) (((n) & 0xf) << 28) |
| #define | BPC_BUFFER_MASK BPC_BUFFER(~0) |
| #define | BPC_BUFFER_0 BPC_BUFFER(0) |
| #define | BPC_BUFFER_1 BPC_BUFFER(1) |
| #define | BPC_BUFFER_2 BPC_BUFFER(2) |
| #define | BPC_BUFFER_3 BPC_BUFFER(3) |
| #define | BPC_BUFFER_4 BPC_BUFFER(4) |
| #define | BPC_BUFFER_5 BPC_BUFFER(5) |
| #define | BPC_BUFFER_6 BPC_BUFFER(6) |
| #define | BPC_BUFFER_7 BPC_BUFFER(7) |
| #define | BPC_BUFFER_NIL BPC_BUFFER(0x8) |
| #define | BPC_PORT(n) (((n) & 0x7) << 25) |
| #define | BPC_PORT_MASK BPC_PORT(~0) |
| #define | BPC_PORT_SERDES BPC_PORT(PORT_SERDES) |
| #define | BPC_PORT_DSP BPC_PORT(PORT_DSP) |
| #define | BPC_PORT_ETH BPC_PORT(PORT_ETH) |
| #define | BPC_PORT_RAM BPC_PORT(PORT_RAM) |
| #define | BPC_PORT_NIL BPC_PORT(0x4) |
| #define | BPC_CLR (1 << 24) |
| #define | BPC_READ (1 << 23) |
| #define | BPC_WRITE (1 << 22) |
| #define | BPC_STEP(step) (((step) & 0xf) << 18) |
| #define | BPC_STEP_MASK BPC_STEP(~0) |
| #define | BPC_LAST_LINE(line) (((line) & 0x1ff) << 9) |
| #define | BPC_LAST_LINE_MASK BPC_LAST_LINE(~0) |
| #define | BPC_FIRST_LINE(line) (((line) & 0x1ff) << 0) |
| #define | BPC_FIRST_LINE_MASK BPC_FIRST_LINE(~0) |
| #define | buffer_pool_ctrl ((buffer_pool_ctrl_t *) BUFFER_POOL_CTRL_BASE) |
| #define | SERDES_ENABLE 8 |
| #define | SERDES_PRBSEN 4 |
| #define | SERDES_LOOPEN 2 |
| #define | SERDES_RXEN 1 |
| #define | ADC_CTRL_ON 0x0F |
| #define | ADC_CTRL_OFF 0x00 |
| #define | LED_A (1 << 4) |
| #define | LED_B (1 << 1) |
| #define | LED_C (1 << 3) |
| #define | LED_D (1 << 0) |
| #define | LED_E (1 << 2) |
| #define | LED_RJ45 (1 << 5) |
| #define | output_regs ((output_regs_t *) MISC_OUTPUT_BASE) |
| #define | MIN_CIC_INTERP 1 |
| #define | MAX_CIC_INTERP 128 |
| #define | dsp_tx_regs ((dsp_tx_regs_t *) DSP_TX_BASE) |
| #define | T_NOW (-1) |
| #define | MIN_CIC_DECIM 1 |
| #define | MAX_CIC_DECIM 128 |
| #define | dsp_rx_regs ((dsp_rx_regs_t *) DSP_RX_BASE) |
| #define | MK_RX_CMD(num_lines, lines_per_frame, now, chain) |
| #define | tx_proto_engine ((tx_proto_engine_regs_t *) TX_PROTOCOL_ENGINE_BASE) |
| #define | rx_proto_engine ((rx_proto_engine_regs_t *) RX_PROTOCOL_ENGINE_BASE) |
| #define | PIC_BASE 0xD800 |
| #define | IRQ_BUFFER 0 |
| #define | IRQ_TIMER 1 |
| #define | IRQ_SPI 2 |
| #define | IRQ_I2C 3 |
| #define | IRQ_PHY 4 |
| #define | IRQ_UNDERRUN 5 |
| #define | IRQ_OVERRUN 6 |
| #define | IRQ_PPS 7 |
| #define | IRQ_UART_RX 8 |
| #define | IRQ_UART_TX 9 |
| #define | IRQ_SERDES 10 |
| #define | IRQ_CLKSTATUS 11 |
| #define | IRQ_TO_MASK(x) (1 << (x)) |
| #define | PIC_BUFFER_INT IRQ_TO_MASK(IRQ_BUFFER) |
| #define | PIC_TIMER_INT IRQ_TO_MASK(IRQ_TIMER) |
| #define | PIC_SPI_INT IRQ_TO_MASK(IRQ_SPI) |
| #define | PIC_I2C_INT IRQ_TO_MASK(IRQ_I2C) |
| #define | PIC_PHY_INT IRQ_TO_MASK(IRQ_PHY) |
| #define | PIC_UNDERRUN_INT IRQ_TO_MASK(IRQ_UNDERRUN) |
| #define | PIC_OVERRUN_INT IRQ_TO_MASK(IRQ_OVERRUN) |
| #define | PIC_PPS_INT IRQ_TO_MASK(IRQ_PPS) |
| #define | PIC_UART_RX_INT IRQ_TO_MASK(IRQ_UART_RX) |
| #define | PIC_UART_TX_INT IRQ_TO_MASK(IRQ_UART_TX) |
| #define | PIC_SERDES IRQ_TO_MASK(IRQ_SERDES) |
| #define | PIC_CLKSTATUS IRQ_TO_MASK(IRQ_CLKSTATUS) |
| #define | pic_regs ((pic_regs_t *) PIC_BASE) |
| #define | TIMER_BASE 0xDC00 |
| #define | timer_regs ((timer_regs_t *) TIMER_BASE) |
| #define | UART_BASE 0xE000 |
| #define | uart_regs ((uart_regs_t *) UART_BASE) |
| #define | ATR_BASE 0xE400 |
| #define | ATR_IDLE 0x0 |
| #define | ATR_TX 0x1 |
| #define | ATR_RX 0x2 |
| #define | ATR_FULL 0x3 |
| #define | atr_regs ((atr_regs_t *) ATR_BASE) |
| #define | TIMESYNC_BASE 0xE800 |
| #define | timesync_regs ((timesync_regs_t *) TIMESYNC_BASE) |
| #define | TSC_SOURCE_PPS (1 << 0) |
| #define | TSC_IENABLE (1 << 1) |
| #define | TSC_EXTSYNC (1 << 2) |
| #define | TSC_PPSEDGE_POS (1 << 3) |
| #define | TSC_TRIGGER_EVERYPPS (1 << 4) |
| #define | SDSPI_BASE 0xEC00 |
| #define | sdspi_regs ((sdspi_regs_t *) SDSPI_BASE) |
| #define | EXTRAM_BASE 0xF000 |
| #define | extram ((volatile uint32_t *) EXTRAM_BASE) |
Functions | |
| static int | hwconfig_simulation_p (void) |
| return non-zero if we're running under the simulator | |
| static int | hwconfig_wishbone_divisor (void) |
| Return Wishbone Clock divisor. The processor runs at the Wishbone Clock rate which is MASTER_CLK_RATE / divisor. | |
Define Documentation
| #define ADC_CTRL_OFF 0x00 |
| #define ADC_CTRL_ON 0x0F |
| #define ATR_BASE 0xE400 |
| #define ATR_FULL 0x3 |
| #define ATR_IDLE 0x0 |
| #define atr_regs ((atr_regs_t *) ATR_BASE) |
| #define ATR_RX 0x2 |
| #define ATR_TX 0x1 |
| #define BP_LAST_LINE (BP_NLINES - 1) |
| #define BP_NLINES 0x0200 |
| #define BPC_BUFFER | ( | n | ) | (((n) & 0xf) << 28) |
Referenced by bp_clear_buf(), bp_receive_to_buf(), and bp_send_from_buf().
| #define BPC_BUFFER_0 BPC_BUFFER(0) |
| #define BPC_BUFFER_1 BPC_BUFFER(1) |
| #define BPC_BUFFER_2 BPC_BUFFER(2) |
| #define BPC_BUFFER_3 BPC_BUFFER(3) |
| #define BPC_BUFFER_4 BPC_BUFFER(4) |
| #define BPC_BUFFER_5 BPC_BUFFER(5) |
| #define BPC_BUFFER_6 BPC_BUFFER(6) |
| #define BPC_BUFFER_7 BPC_BUFFER(7) |
| #define BPC_BUFFER_MASK BPC_BUFFER(~0) |
| #define BPC_BUFFER_NIL BPC_BUFFER(0x8) |
Referenced by bp_disable_port().
| #define BPC_CLR (1 << 24) |
Referenced by bp_clear_buf().
| #define BPC_FIRST_LINE | ( | line | ) | (((line) & 0x1ff) << 0) |
Referenced by bp_receive_to_buf(), and bp_send_from_buf().
| #define BPC_FIRST_LINE_MASK BPC_FIRST_LINE(~0) |
| #define BPC_LAST_LINE | ( | line | ) | (((line) & 0x1ff) << 9) |
Referenced by bp_receive_to_buf(), and bp_send_from_buf().
| #define BPC_LAST_LINE_MASK BPC_LAST_LINE(~0) |
| #define BPC_PORT | ( | n | ) | (((n) & 0x7) << 25) |
Referenced by bp_disable_port(), bp_receive_to_buf(), and bp_send_from_buf().
| #define BPC_PORT_DSP BPC_PORT(PORT_DSP) |
| #define BPC_PORT_ETH BPC_PORT(PORT_ETH) |
| #define BPC_PORT_MASK BPC_PORT(~0) |
| #define BPC_PORT_NIL BPC_PORT(0x4) |
Referenced by bp_clear_buf().
| #define BPC_PORT_RAM BPC_PORT(PORT_RAM) |
| #define BPC_PORT_SERDES BPC_PORT(PORT_SERDES) |
| #define BPC_READ (1 << 23) |
Referenced by bp_receive_to_buf().
| #define BPC_STEP | ( | step | ) | (((step) & 0xf) << 18) |
Referenced by bp_receive_to_buf(), and bp_send_from_buf().
| #define BPC_STEP_MASK BPC_STEP(~0) |
| #define BPC_WRITE (1 << 22) |
Referenced by bp_send_from_buf().
| #define BPS_DONE | ( | n | ) | (0x00000001 << (n)) |
| #define BPS_DONE_0 BPS_DONE(0) |
| #define BPS_DONE_1 BPS_DONE(1) |
| #define BPS_DONE_2 BPS_DONE(2) |
| #define BPS_DONE_3 BPS_DONE(3) |
| #define BPS_DONE_4 BPS_DONE(4) |
| #define BPS_DONE_5 BPS_DONE(5) |
| #define BPS_DONE_6 BPS_DONE(6) |
| #define BPS_DONE_7 BPS_DONE(7) |
| #define BPS_DONE_ALL 0x000000ff |
| #define BPS_ERROR | ( | n | ) | (0x00000100 << (n)) |
| #define BPS_ERROR_0 BPS_ERROR(0) |
| #define BPS_ERROR_1 BPS_ERROR(1) |
| #define BPS_ERROR_2 BPS_ERROR(2) |
| #define BPS_ERROR_3 BPS_ERROR(3) |
| #define BPS_ERROR_4 BPS_ERROR(4) |
| #define BPS_ERROR_5 BPS_ERROR(5) |
| #define BPS_ERROR_6 BPS_ERROR(6) |
| #define BPS_ERROR_7 BPS_ERROR(7) |
| #define BPS_ERROR_ALL 0x0000ff00 |
| #define BPS_IDLE | ( | n | ) | (0x00010000 << (n)) |
| #define BPS_IDLE_0 BPS_IDLE(0) |
| #define BPS_IDLE_1 BPS_IDLE(1) |
| #define BPS_IDLE_2 BPS_IDLE(2) |
| #define BPS_IDLE_3 BPS_IDLE(3) |
| #define BPS_IDLE_4 BPS_IDLE(4) |
| #define BPS_IDLE_5 BPS_IDLE(5) |
| #define BPS_IDLE_6 BPS_IDLE(6) |
| #define BPS_IDLE_7 BPS_IDLE(7) |
| #define BPS_IDLE_ALL 0x00ff0000 |
| #define BPS_SLOWPATH | ( | n | ) | (0x01000000 << (n)) |
| #define BPS_SLOWPATH_0 BPS_SLOWPATH(0) |
| #define BPS_SLOWPATH_1 BPS_SLOWPATH(1) |
| #define BPS_SLOWPATH_2 BPS_SLOWPATH(2) |
| #define BPS_SLOWPATH_3 BPS_SLOWPATH(3) |
| #define BPS_SLOWPATH_4 BPS_SLOWPATH(4) |
| #define BPS_SLOWPATH_5 BPS_SLOWPATH(5) |
| #define BPS_SLOWPATH_6 BPS_SLOWPATH(6) |
| #define BPS_SLOWPATH_7 BPS_SLOWPATH(7) |
| #define BPS_SLOWPATH_ALL 0xff000000 |
| #define buffer_pool_ctrl ((buffer_pool_ctrl_t *) BUFFER_POOL_CTRL_BASE) |
Referenced by bp_clear_buf(), bp_disable_port(), bp_receive_to_buf(), and bp_send_from_buf().
| #define BUFFER_POOL_CTRL_BASE 0xD500 |
| #define buffer_pool_ram ((uint32_t *) BUFFER_POOL_RAM_BASE) |
| #define BUFFER_POOL_RAM_BASE 0x8000 |
| #define buffer_pool_status ((buffer_pool_status_t *) BUFFER_POOL_STATUS_BASE) |
Referenced by hwconfig_simulation_p(), and hwconfig_wishbone_divisor().
| #define BUFFER_POOL_STATUS_BASE 0xCC00 |
| #define buffer_ram | ( | n | ) | (&buffer_pool_ram[(n) * BP_NLINES]) |
| #define DSP_RX_BASE 0xD680 |
| #define dsp_rx_regs ((dsp_rx_regs_t *) DSP_RX_BASE) |
| #define DSP_TX_BASE 0xD600 |
| #define dsp_tx_regs ((dsp_tx_regs_t *) DSP_TX_BASE) |
| #define ETH_BASE 0xD000 |
| #define eth_mac ((eth_mac_regs_t *) ETH_BASE) |
| #define extram ((volatile uint32_t *) EXTRAM_BASE) |
| #define EXTRAM_BASE 0xF000 |
| #define GPIO_BASE 0xC800 |
| #define gpio_base ((gpio_regs_t *) GPIO_BASE) |
| #define GPIO_SEL_ATR 1 |
| #define GPIO_SEL_DEBUG_0 2 |
| #define GPIO_SEL_DEBUG_1 3 |
| #define GPIO_SEL_SW 0 |
| #define HWC_SIMULATION 0x80000000 |
Referenced by hwconfig_simulation_p().
| #define HWC_WB_CLK_DIV_MASK 0x0000000f |
Referenced by hwconfig_wishbone_divisor().
| #define I2C_BASE 0xC400 |
| #define I2C_CMD_IACK (1 << 0) |
| #define I2C_CMD_NACK (1 << 3) |
| #define I2C_CMD_RD (1 << 5) |
| #define I2C_CMD_RSVD_1 (1 << 1) |
| #define I2C_CMD_RSVD_2 (1 << 2) |
| #define I2C_CMD_START (1 << 7) |
| #define I2C_CMD_STOP (1 << 6) |
| #define I2C_CMD_WR (1 << 4) |
| #define I2C_CTRL_EN (1 << 7) |
| #define I2C_CTRL_IE (1 << 6) |
| #define i2c_regs ((i2c_regs_t *) I2C_BASE) |
| #define I2C_ST_AL (1 << 5) |
| #define I2C_ST_BUSY (1 << 6) |
| #define I2C_ST_IP (1 << 0) |
| #define I2C_ST_RSVD_2 (1 << 2) |
| #define I2C_ST_RSVD_3 (1 << 3) |
| #define I2C_ST_RSVD_4 (1 << 4) |
| #define I2C_ST_RXACK (1 << 7) |
| #define I2C_ST_TIP (1 << 1) |
| #define IRQ_BUFFER 0 |
| #define IRQ_CLKSTATUS 11 |
| #define IRQ_I2C 3 |
| #define IRQ_OVERRUN 6 |
| #define IRQ_PHY 4 |
| #define IRQ_PPS 7 |
| #define IRQ_SERDES 10 |
| #define IRQ_SPI 2 |
| #define IRQ_TIMER 1 |
| #define IRQ_TO_MASK | ( | x | ) | (1 << (x)) |
| #define IRQ_UART_RX 8 |
| #define IRQ_UART_TX 9 |
| #define IRQ_UNDERRUN 5 |
| #define LAST_SETTING_REG 0xD7FC |
| #define LED_A (1 << 4) |
| #define LED_B (1 << 1) |
| #define LED_C (1 << 3) |
| #define LED_D (1 << 0) |
| #define LED_E (1 << 2) |
| #define LED_RJ45 (1 << 5) |
| #define MASTER_CLK_RATE 100000000 |
| #define MAX_CIC_DECIM 128 |
| #define MAX_CIC_INTERP 128 |
| #define MIN_CIC_DECIM 1 |
| #define MIN_CIC_INTERP 1 |
| #define MISC_OUTPUT_BASE 0xD400 |
| #define MK_RX_CMD | ( | num_lines, | |
| lines_per_frame, | |||
| now, | |||
| chain | |||
| ) |
Value:
(((num_lines) << 9) | ((lines_per_frame) & 0x1ff) \ | (((now) & 0x1) << 31) | (((chain) & 0x1) << 30))
| #define NBUFFERS 8 |
| #define output_regs ((output_regs_t *) MISC_OUTPUT_BASE) |
| #define PIC_BASE 0xD800 |
| #define PIC_BUFFER_INT IRQ_TO_MASK(IRQ_BUFFER) |
| #define PIC_CLKSTATUS IRQ_TO_MASK(IRQ_CLKSTATUS) |
| #define PIC_I2C_INT IRQ_TO_MASK(IRQ_I2C) |
| #define PIC_OVERRUN_INT IRQ_TO_MASK(IRQ_OVERRUN) |
| #define PIC_PHY_INT IRQ_TO_MASK(IRQ_PHY) |
| #define PIC_PPS_INT IRQ_TO_MASK(IRQ_PPS) |
| #define pic_regs ((pic_regs_t *) PIC_BASE) |
| #define PIC_SERDES IRQ_TO_MASK(IRQ_SERDES) |
| #define PIC_SPI_INT IRQ_TO_MASK(IRQ_SPI) |
| #define PIC_TIMER_INT IRQ_TO_MASK(IRQ_TIMER) |
| #define PIC_UART_RX_INT IRQ_TO_MASK(IRQ_UART_RX) |
| #define PIC_UART_TX_INT IRQ_TO_MASK(IRQ_UART_TX) |
| #define PIC_UNDERRUN_INT IRQ_TO_MASK(IRQ_UNDERRUN) |
| #define PORT_DSP 1 |
| #define PORT_ETH 2 |
| #define PORT_RAM 3 |
| #define PORT_SERDES 0 |
| #define RAM_BASE 0x0000 |
| #define rx_proto_engine ((rx_proto_engine_regs_t *) RX_PROTOCOL_ENGINE_BASE) |
| #define RX_PROTOCOL_ENGINE_BASE 0xD4C0 |
| #define SDSPI_BASE 0xEC00 |
| #define sdspi_regs ((sdspi_regs_t *) SDSPI_BASE) |
Referenced by sd_assert_cs(), sd_deassert_cs(), sd_rcv_byte(), and sd_send_byte().
| #define SERDES_ENABLE 8 |
| #define SERDES_LOOPEN 2 |
| #define SERDES_PRBSEN 4 |
| #define SERDES_RXEN 1 |
| #define SPI_BASE 0xC000 |
| #define SPI_CTRL_ASS (1<<13) |
| #define SPI_CTRL_CHAR_LEN_MASK 0x7F |
| #define SPI_CTRL_GO_BSY (1<< 8) |
| #define SPI_CTRL_IE (1<<12) |
| #define SPI_CTRL_LSB (1<<11) |
| #define SPI_CTRL_RXNEG (1<< 9) |
| #define SPI_CTRL_TXNEG (1<<10) |
| #define spi_regs ((spi_regs_t *) SPI_BASE) |
| #define SPI_SS_AD9510 1 |
| #define SPI_SS_AD9777 2 |
| #define SPI_SS_RX_ADC 8 |
| #define SPI_SS_RX_DAC 4 |
| #define SPI_SS_RX_DB 16 |
| #define SPI_SS_TX_ADC 64 |
| #define SPI_SS_TX_DAC 32 |
| #define SPI_SS_TX_DB 128 |
| #define T_NOW (-1) |
| #define TIMER_BASE 0xDC00 |
| #define timer_regs ((timer_regs_t *) TIMER_BASE) |
Referenced by hal_set_timeout().
| #define TIMESYNC_BASE 0xE800 |
| #define timesync_regs ((timesync_regs_t *) TIMESYNC_BASE) |
| #define TSC_EXTSYNC (1 << 2) |
| #define TSC_IENABLE (1 << 1) |
| #define TSC_PPSEDGE_POS (1 << 3) |
| #define TSC_SOURCE_PPS (1 << 0) |
| #define TSC_TRIGGER_EVERYPPS (1 << 4) |
| #define tx_proto_engine ((tx_proto_engine_regs_t *) TX_PROTOCOL_ENGINE_BASE) |
| #define TX_PROTOCOL_ENGINE_BASE 0xD480 |
| #define UART_BASE 0xE000 |
| #define uart_regs ((uart_regs_t *) UART_BASE) |
Function Documentation
| static int hwconfig_simulation_p | ( | void | ) | [inline, static] |
return non-zero if we're running under the simulator
References buffer_pool_status, and HWC_SIMULATION.
| static int hwconfig_wishbone_divisor | ( | void | ) | [inline, static] |
Return Wishbone Clock divisor. The processor runs at the Wishbone Clock rate which is MASTER_CLK_RATE / divisor.
References buffer_pool_status, and HWC_WB_CLK_DIV_MASK.
